HRR-10102: Synchronous Clears

Synchronous clear signals may limit the performance of designs using the Intel® Hyperflex™ architecture.

Recommendation

Remove synchronous clear signals if a circuit naturally resets when reset is held long enough to reach steady-state equivalent of a full reset. For more information about the recommended techniques to achieve maximum performance when using reset signals, refer to the Intel® Stratix® 10 High-Performance Design Handbook.

Severity

Medium

Stage

Analysis and Elaboration

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™