HRR-10101: Asynchronous Clears
Asynchronous clear signals always prevent the Intel® Quartus® Prime Pro Edition software from retiming paths in designs using the
Intel® Hyperflex™ architecture, limiting the speed at
which the designs can be operated.
Recommendation
Remove asynchronous clear if the circuit naturally resets when the reset is held long enough to reach a steady-state equivalent of a full reset.
Severity
Medium
Stage
Analysis and Elaboration
Device Family
- Intel® Stratix® 10
- Intel® Agilex™