Performing a Timing Simulation with the VCS Software

To perform a timing simulation of a Intel^® Quartus^® Prime generated Verilog Output File (.vo) Definition and the corresponding with the Synopsys^® VCS software:

If you have not already done so, perform set up the VCS Working Environment.
Include the Intel^® Quartus^® Prime-generated Verilog Design File (.v) Definition in the testbench file:
```
include <testbench or design instance name>_dump_all_vcd_nodes.v
```
The Verilog Design File directs the VCS software to monitor and write the output signals contained in the Verilog Design File to a VCD file during simulation.
You later use this Value Change Dump File (.vcd) Definition to perform power analysis in the Intel^® Quartus^® Prime Power Analyzer).
Compile the Verilog Output File with the VCS software with one of the following commands typed at the command prompt.
To generate a simv.exe file, which you can use later to simulate the design:
vcs <testbench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf
To compile the Verilog Output File with the VCS software and simulate it automatically:
vcs -R <testbench>.v <design name>.vo -v \quartus\eda\sim_lib\<device family>_atoms.v +compsdf

Note:

The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify the Stratix^® V or newer device families, even if you specified a timing simulation netlist.

Important:

If your design contains high-speed elements such as GXB blocks, you must use transport delay options to perform a timing simulation. You can add transport delay options for the VCS software when performing a timing simulation with . For more information on using transport delays, see the Synopsys^® VCS and VCS-MX Support chapter in the Intel^® Quartus^® Prime Handbook, Volume 3.
Intel recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulations of designs with RAM.