In the design contained in the following diagram, the AND labeled gate_1 feeds two registers, reg_1 and reg_2.
The Design Assistant reports that gate_1 violates the Gated clock should be implemented according to Altera standard scheme (C101) rule. Suppressing the rule on the reported nodegate_1disables violation reporting on bothreg_1andreg_2. Likewise, suppressing the rule on bothreg_1andreg_2also disables violation reporting forgate_1. In order for Design Assistant to report when one of the two registers causes a rule violation, you should suppress eitherreg_1orreg_2, but not both.