Register Output Should Not Drive Its Own Control Signal Directly or Through Combinational Logic (Design Assistant Rule)

A design should not contain any combinational loops where the output of a register directly drives one of its own control signals (for example, the register's preset signal or asynchronous load signal), or the output of the register drives combinational logic that drives one of the register's control signals.

The following image shows an example of a combinational loop where the output of a register directly drives one of its own control signals:





The following image shows an example of a combinational loop where the output of a register drives combinational logic that drives one of the register's control signals:





These combinational loops can cause significant stability and reliability problems in a design. For example, because the behavior of a combinational loop often depends on the relative propagation delays of the combinational loop's logic, and because design tools experience difficulties when handling combinational loops, the combinational loop after fitting may not function as it was originally intended to function in the design.

Important: Important: This rule can be turned on or off as a global setting for the entire design on the Design Assistant page; or enabled or disabled for nodes, entities, or instances with Rule A102. This rule has a Critical severity level.