Performing a Functional Simulation with the Riviera-PRO Software

You can use the Aldec Riviera-PRO software to perform an RTL functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components.

Note:

In addition to its native command-line commands, the Riviera-PRO software also supports ModelSim command-line commands. In the following steps, the ModelSim commands are the commands that start with "v", such as vlib.

If you have not already done so, set up the Riviera-PRO working environment.
Start the simulator in command-line mode from the / <Riviera_PRO root directory> /runvsimsa.bat file (Windows) or the runvsimsa script (Linux).
To create a working library, type the following command: alib/vlib < library name >
To set the value of the worklib variable, type the following command: set worklib < library name >

The working library is typically called work.
To map the logical name to the library index, type the following command: amap/vmap < library name >
To compile the Verilog HDL or VHDL simulation library files:
1. To create a library for the simulation library files, type the following command: alib/vlib < simulation library name >
2. Choose the necessary simulation model files provided with the Quartus^® Prime Standard Editionsoftware for your design.
3. To compile the files chosen in the previous step, type: alog/vlog/acom/vcom -dbg -work < simulation library name > < file name > If you do not need to debug your design, you should compile the source files without the -dgb switch, which can decrease simulation speed.
To compile the Verilog HDL or VHDL design and test bench files, type the following command: alog/vlog/acom/vcom -dbg -work < library name > < file name > If you do not need to debug your design, you should compile the source files without the -dgb switch, which can decrease simulation speed.

To initialize the simulation, type the following command: asim/vsim -t 1ps -L < library1 > -L < library2 > ... < top module >

Switch/Argument	Description
`-t`	Defines the time scale to be simulated in ps
`-L`	Allows you to specify multiple simulation libraries that you already compiled

Note:

Once you initialize the simulation in this step, the simulation database (.asdb file) is created.

To run the simulation, type the following command: run < running time >

To run the simulation until the end, leave out the <running time> argument.

Note: Use the command transcript file<file name> to record messages.

Note: For more information about using EDA simulators, refer to Aldec Active-HDL and Riviera-PRO Support in the Quartus^® Prime Standard Edition Handbook.

To continue with the Riviera-PRO simulation flow, perform a post-synthesis simulation with the Riviera-PRO software.